Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis

Nowadays, clock skew becomes a manageable resource to improve circuits by assigning a certain clock delay to each register. However, it has been reported that implementing a large spectrum of dedicated clock delays becomes challenging in a reliable manner under several uncertainties. To overcome this limitation, multi-domain clock skew scheduling (MDCSS) has been proposed, and studied in logic- and physical-level design stages. This paper firstly introduce the concept of MDCSS into high-level synthesis, and shows that register binding and domain assignment have a significant impact on the performance of the resulting datapath. A mixed integer linear program model to optimize MDCSS-based datapath is presented, which can be used for various objectives in MDCSS-based design. Experiments on several benchmark circuits validate the effectiveness of the approach.