Concordant memory-array design: an integrated statistical approach for high quality gigabit-DRAM design

A concordant memory-array design incorporates device fluctuation statistically into the signal-to-noise ratio analysis in DRAM and represents the failed bits in a chip. The proposed technique gives us a quantitative evaluation of the memory array and assures the operation of the 1.4 V array of a 100 nm - 1 Gb DRAM. The calculated dependence of failed bit counts on the array voltage is in good agreement with the experimental results of a 512 Mbit DRAM chip.