Proximity effects and VLSI design

The authors have presented the data illustrating several proximity effects - layout variations that affect transistor characteristics. Some of these proximity effects may be best avoided by layout groundrules (polysilicon doping, butted junction proximity). Others (well and halo proximity, isolation size) are accommodated by including the effect in the compact model. None of these effects is likely to be completely eliminated in principle, so designers should become familiar with the nature of these effects, and be prepared to take them into account in circuit layouts.