DocumentCode
1893802
Title
A study of deadbeat control for three phase PWM inverter using FPGA based hardware controller
Author
Ide, Toshihiro ; Yokoyama, Tomoki
Author_Institution
Tokyo Denki Univ., Saitama, Japan
Volume
1
fYear
2004
fDate
20-25 June 2004
Firstpage
50
Abstract
A new method for the real-time digital feedback control for three phase PWM inverter is proposed, in which realizes a deadbeat control using FPGA based hardware controller. In recent years, large-scale and high-speed FPGAs make it possible to realize complicated control calculation with very high speed execution time. Calculation time for FPGA depends on the circuit design, especially how to construct the parallel processing circuit in the chip. Moreover, the latest FPGA contain embedded RAM, CPU core, DSP block, and it is possible to design a highspeed calculation circuit simply. Up to now, the digital feedback inverter control constructed by the software controller using DSP. DSP software is treated as a sequential process, so some calculation time is necessary. Since the finite time is required for the control calculation after measuring signals, it is impossible to realize the control law which use the k´s sampling data to the k´s control output. On the other hand, using FPGA based hardware controller, parallel processing can be realized. As the result, FPGA based control system makes it possible to realize the digital control system with negligible sampling delay and calculation time delay. In this paper, an instantaneous deadbeat control for three phase PWM inverter using FPGA based hardware controller is proposed. All the control calculation block, AD interface block and pulse pattern generation block are implemented in one FPGA chip. The characteristics of the proposed control method were verified through simulations and experiments. A design concept of the experimental system is also proposed.
Keywords
PWM invertors; analogue-digital conversion; digital control; digital signal processing chips; field programmable gate arrays; pulse generators; AD interface block; DSP software; FPGA chip; control calculation block; deadbeat control; field programmable gate arrays; hardware controller; parallel processing circuit; pulse pattern generation block; real-time digital feedback control; three phase PWM inverter; Circuits; Delay effects; Digital control; Digital signal processing chips; Feedback control; Field programmable gate arrays; Hardware; Large-scale systems; Parallel processing; Pulse width modulation inverters;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual
ISSN
0275-9306
Print_ISBN
0-7803-8399-0
Type
conf
DOI
10.1109/PESC.2004.1355712
Filename
1355712
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