SOI partially-depleted ultra low voltage memory and digital circuit design

In this paper the authors investigated design techniques for ultra low voltage (ULV) SRAM and digital circuits based on partially-depleted silicon on insulator (SOI) devices. A systematic design methodology dedicated to SRAM memory cells is presented, it takes into account the floating body effect at different levels of the design process. This methodology is used to design a new 4 transistors self-refresh memory cell and results are compared to the 6 transistors one. ULV digital circuits, ranging from basic gates to a complex wavelet transform are investigated. It is shown that for 130nm SOI partially-depleted technology that using high-speed transistors leads to a significant speed improvement and power saving. The power-delay product is improved by a factor of 2.4.