A CMOS imager for embedded systems with integrated, real-time, motion-detection capabilities and digital output

A CMOS, smart, low-power imager with pre-processing capabilities suitable for embedded systems, was realized and successfully tested. The chip hosts an array of 64times64 active pixels for image acquisition and frame storage, a programmable and reconfigurable analog row-processor for parallel spatial and temporal filtering of an image row at the time and a fully digital communication block for chip configuration and frame grabbing. The row processor is capable of implementing programmable and tunable 2D spatial IIR filters and programmable temporal FIR filters with up to 8 taps. The two computations may be cascaded on-chip in order to extract motion information in real-time. The same row-processor can be reconfigured into a parallel set of 64 8-bit A/D converters to achieve fully digital read-out. The chip was fabricated in a 0.35 um process by AMI Semiconductors, has a size of 6 mm², hosts 120,000 transistors with a static power consumption of 4.7 mW and is capable of a frame rate of 50 frames/sec.