Low-voltage embedded RAMs in the nanometer era

Author

Itoh, Kenji

Author_Institution

Central Res. Lab., Hitachi, Ltd., Tokyo, Japan

fYear

2005

fDate

9-11 May 2005

Firstpage

235

Lastpage

242

Abstract

Low-voltage high-density embedded RAMs (e-RAMs) in the nanometer era are described, with a focus on RAM cells and peripheral circuits. First, challenges and trends in low-voltage e-RAMs are described based on the signal-to-noise ratio problem of RAM cells, then leakage and speed-variation problems of peripheral circuits. Next, state-of-the-art low-voltage e-DRAMs and e-SRAMs are investigated, mainly focusing on cell structures and leakage-reduction circuits. Finally, future prospects for low-voltage e-RAMs are discussed.

Keywords

cellular arrays; embedded systems; leakage currents; low-power electronics; random-access storage; embedded DRAM; embedded RAM; embedded SRAM; leakage reduction circuits; nanometer electronics; peripheral circuits; signal to noise ratio; speed variation; Capacitance; Circuits; Degradation; Laboratories; Maintenance; Power dissipation; Power supplies; Random access memory; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Print_ISBN

0-7803-9081-4

Type

conf

DOI

10.1109/ICICDT.2005.1502639

Filename

1502639

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1894025