A CMOS fractional-N frequency synthesizer for low-power RF applications

Author

Sharaf, Khaled M.

Author_Institution

Dept. of Electr. Eng., Ain-Shams Univ., Cairo, Egypt

fYear

2002

fDate

2002

Firstpage

527

Lastpage

531

Abstract

A divider-free fractional-N CMOS frequency locked loop synthesizer is presented. The frequency divider used in traditional frequency synthesizers is replaced by a switched-capacitor frequency detector (SC-FD). The architecture of the proposed synthesizer has been successfully simulated at behavioral level to verify its expected functionality. Design considerations of various synthesizer building blocks are discussed to highlight their impact on the synthesizer performance.

Keywords

CMOS integrated circuits; circuit simulation; field effect MMIC; frequency synthesizers; integrated circuit design; integrated circuit modelling; low-power electronics; phase locked loops; switched capacitor networks; FLL; RF frequency synthesizers; SC-FD; behavior modeling; behavioral level simulation; divider-free fractional-N CMOS frequency locked loop synthesizer; fractional-N PLL; frequency divider; frequency locked loop; low-power RF applications; phase locked loop; switched capacitor frequency detector; synthesizer architecture; synthesizer building block design considerations; synthesizer functionality; synthesizer performance; Channel spacing; Circuit simulation; Frequency conversion; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Radio frequency; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean

Print_ISBN

0-7803-7527-0

Type

conf

DOI

10.1109/MELECON.2002.1014648

Filename

1014648