A 1.8V/5.2GHz WLAN CMOS RFIC receiver

Author

Azevedo, Fernando ; Fortes, Fernando ; Rosário, Maria João

Author_Institution

Inst. de Telecomun., Inst. Super. Tecnico, Lisbon, Portugal

fYear

2011

fDate

27-29 April 2011

Firstpage

1

Lastpage

4

Abstract

This paper describes a low-cost 1.8V/5.2GHz monolithic Zero-IF receiver. All of the RF and conversion receiver components, with the exception of the frequency synthesizer, have been integrated into a single chip solution. The circuit is implemented in a 0.18μm CMOS technology and is suitable for WLAN applications. Is optimized to noise performance, gain and differential mismatches. At 5.2GHz the system simulations shows NF=3.7dB, 1dB_CP = -22dBm and IIP3 = -10dBm. In a 200MHz span around 5.2GHz the power gain is higher then 25dB and the phase and gain mismatches lower than 7° and 0.1dB, while drawing 20mA from a 1.8V power supply.

Keywords

CMOS integrated circuits; field effect MMIC; frequency synthesizers; radio receivers; radiofrequency integrated circuits; wireless LAN; CMOS RFIC receiver; current 20 mA; frequency 5.2 GHz; frequency synthesizer; monolithic zero-IF receiver; noise figure 3.7 dB; size 0.18 mum; voltage 1.8 V; wireless LAN; Gain; Impedance matching; Mixers; Noise measurement; Radio frequency; Receivers; Topology; CMOS; RFIC; Receiver; Wireless Communications; front-end;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROCON - International Conference on Computer as a Tool (EUROCON), 2011 IEEE

Conference_Location

Lisbon

Print_ISBN

978-1-4244-7486-8

Type

conf

DOI

10.1109/EUROCON.2011.5929392

Filename

5929392