Title :
Robust optimization of serial link system for signal integrity and power integrity
Author :
Tripathi, Jai Narayan ; Nagpal, Raj Kumar ; Malik, Rakesh
Author_Institution :
Dept. of EE, IIT Bombay, Mumbai, India
Abstract :
Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK taking into account the external parameters like board, package, measurement environment which influence the performance of the channel. Parameters variations appearing from manufacturability constraints, material property constraints, design tolerance etc affecting the serial link performance has been optimized using Taguchi method based on statistical co-analysis. Using the Taguchi statistical techniques, sensitivity analysis on parameter variations affecting HSLINK performance is analyzed and optimized for desired performance.
Keywords :
Taguchi methods; error statistics; peripheral interfaces; power supplies to apparatus; statistical analysis; Taguchi method; Taguchi statistical techniques; USB HSLINK performance; bit error rate; design tolerance; manufacturability constraints; power integrity; serial link performance; serial link system optimization; signal integrity; statistical co-analysis; system level model; termination environment; Bit error rate; Jitter; Noise; Optimization; Robustness; Silicon; Universal Serial Bus; Bit error Rate (BER); High Speed Data Transmission; Power Integrity; Robust Optimization; Serial links; Signal Integrity; Taguchi Methods;
Conference_Titel :
Networked Embedded Systems for Enterprise Applications (NESEA), 2010 IEEE International Conference on
Conference_Location :
Suzhou
Print_ISBN :
978-1-4244-9178-0
Electronic_ISBN :
978-1-4244-9176-6
DOI :
10.1109/NESEA.2010.5678052