A salicide-bridged trench capacitor with a double-sacrificial-Si/sub 3/N/sub 4/-sidewall (DSS) for high-performance logic-embedded DRAMs

Author

Togo, M. ; Iwao, S. ; Nobusawa, H. ; Hamada, M. ; Yoshida, K. ; Yasuzato, N. ; Tanigawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

37

Lastpage

40

Abstract

We propose a Double-Sacrificial-Si/sub 3/N/sub 4/-Sidewall (DSS) technology to develop a salicide-bridged trench-capacitor cell for high-performance logic-embedded DRAMs. Both the DSS technology and the salicide-bridging are fully compatible with high-performance CMOS processes. With these technologies, a storage node of a Substrate-Plate Trench (SPT) capacitor can be connected to a drain node even over a thick oxide collar during the silicidation.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; MIS capacitors; integrated circuit technology; Si/sub 3/N/sub 4/; double-sacrificial-Si/sub 3/N/sub 4/-sidewall; high-performance CMOS processes; logic-embedded DRAMs; salicide-bridged trench capacitor; silicidation; substrate-plate trench capacitor; Bridge circuits; CMOS technology; Capacitance; Capacitors; Decision support systems; Dielectric films; Leakage current; MOSFETs; Random access memory; Silicidation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649450

Filename

649450