Early Functional Evaluation of SET Effects

Fault injection in VHDL descriptions has become an efficient solution to analyze at an early stage of the design the potential faulty behaviors of a complex digital circuit. Classical injection campaigns are based on the "single bit-flip" fault model, representative of single event upsets (SEUs). Single event transients (SETs) are becoming more important with very deep sub-micron technologies and require different early analyses strategies. This paper discusses the new requirements and proposes an approach to automate early fault injections targeted towards SET effects.