Title :
The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology
Author :
Hutson, John M. ; Schrimpf, R.D. ; Massengill, L.M.
Author_Institution :
Vanderbilt Univ., Nashville
Abstract :
TCAD simulations are performed to examine the effects of scaling, well and substrate contact spacing, and supply voltage ( Vdd) on the vulnerability of devices to single-event latchup in bulk CMOS from 65-nm to 250-nm technologies. The effects of substrate depth are also shown to play a role in the sensitivity.
Keywords :
CMOS integrated circuits; technology CAD (electronics); TCAD simulations; bulk CMOS technology; scaling effects; single event latchup; substrate contact placement; substrate depth; Bipolar transistors; CMOS technology; Circuit topology; Contacts; Discrete event simulation; Doping; Physics; Predictive models; Threshold voltage; Variable structure systems;
Conference_Titel :
Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on
Conference_Location :
Cap d´Agde
Print_ISBN :
978-0-7803-9502-2
Electronic_ISBN :
0379-6566
DOI :
10.1109/RADECS.2005.4365577
