A High-Speed BiCMOS Fully Differential Operational Amplifier with Improved Slew Rate and Phase Margin

Author

Mu, Feiyan ; Wang, Can ; Lin, Jie

Author_Institution

Dept. of Electron. Eng., Chengdu Coll. of UESTC, Chengdu, China

Volume

1

fYear

2012

fDate

23-25 March 2012

Firstpage

652

Lastpage

655

Abstract

A high-gain high-speed fully differential folded-cascade operational amplifier with improved slew rate (SR) is implemented in a 0.6-μm SiGe BiCMOS process. The amplifier can source/sink much larger current than the quiescent current when output voltage is slewing, even with a current reduction in the common-base path. Compared to the CMOS folded-cascode configuration, BiCMOS folded-cascode improves the phase margin. Cadence Spectre simulation shows that the amplifier has an open-loop DC gain of 103 dB, a unit gain bandwidth of 270 MHz and a phase margin of 63° degrees and a slew rate of 1265 V/μs only consuming 1.6 mA in the main amplifier path, all with 4 pF capacitive loading.

Keywords

BiCMOS analogue integrated circuits; Ge-Si alloys; differential amplifiers; operational amplifiers; BiCMOS folded-cascode configuration; SiGe; bandwidth 270 MHz; capacitance 4 pF; current 1.8 mA; gain 103 dB; high-speed BiCMOS fully differential operational amplifier; open-loop DC gain; phase margin; quiescent current; size 0.6 mum; slew rate; voltage 1265 V; BiCMOS integrated circuits; Bipolar transistors; Gain; MOSFETs; Operational amplifiers; Power demand; BiCMOS process; fully differential; operational amplifier; pipeline ADC; slew rate component;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Electronics Engineering (ICCSEE), 2012 International Conference on

Conference_Location

Hangzhou

Print_ISBN

978-1-4673-0689-8

Type

conf

DOI

10.1109/ICCSEE.2012.4

Filename

6187863