DocumentCode :
1895303
Title :
Trade-offs in the integration of high performance devices with trench capacitor DRAM
Author :
Crowder, S. ; Stiffler, S. ; Parries, P. ; Bronner, G. ; Nesbit, L. ; Wille, W. ; Powell, M. ; Ray, A. ; Chen, B. ; Davari, B.
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
fYear :
1997
fDate :
10-10 Dec. 1997
Firstpage :
45
Lastpage :
48
Abstract :
This paper demonstrates it is possible to enhance the device performance of a standard DRAM process by 35% with only a moderate reduction in retention time. We have also merged high-performance logic devices and working DRAM at the cost of an appreciable degradation in retention behavior and a slightly larger cell. The device performance is 1.82/spl times/ the base process. This demonstrates that embedding DRAM in a high-performance technology is feasible although the optimum trade-off between performance, density, retention time, cost, and power depends on the application.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; integrated circuit technology; embedded DRAM; high performance devices; logic devices; retention time; trench capacitor DRAM; Capacitors; Cost function; Degradation; Drives; Logic devices; Random access memory; Research and development; Standards development; Substrates; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4100-7
Type :
conf
DOI :
10.1109/IEDM.1997.649452
Filename :
649452
Link To Document :
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