DocumentCode :
1895504
Title :
Bare chip test techniques for multichip modules
Author :
Fillion, R.A. ; Wojnarowski, R.J. ; Daum, W.
Author_Institution :
GE Corporate Res. & Dev. Center, Schenectady, NY, USA
fYear :
1990
fDate :
20-23 May 1990
Firstpage :
554
Abstract :
A unique bare-chip test methodology has been developed based upon the GE high-density interconnect (HDI) technology. This methodology allows at-speed testing and screening of complex ASICs (application-specific integrated circuits) and microprocessor chips over the full military temperature range in standard chip-carrier test sockets without any special fixturing or probe cards or in clusters of common chips in a test array. The authors describe the HDI packaging approach and how it is being utilized to perform bare-ship pretest of RAM chips, processors, and complex ASICs and how it can be utilized to provide full preassembly burn-in
Keywords :
application specific integrated circuits; integrated circuit testing; integrated memory circuits; microprocessor chips; modules; random-access storage; GE high-density interconnect; RAM chips; at-speed testing; bare-chip test methodology; bare-ship pretest; clusters; complex ASICs; microprocessor chips; military temperature range; multichip modules; preassembly burn-in; screening; standard chip-carrier test sockets; Application specific integrated circuits; Circuit testing; Integrated circuit interconnections; Integrated circuit technology; Integrated circuit testing; Microprocessor chips; Military standards; Multichip modules; Sockets; Temperature distribution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1990. ., 40th
Conference_Location :
Las Vegas, NV
Type :
conf
DOI :
10.1109/ECTC.1990.122242
Filename :
122242
Link To Document :
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