Title :
A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS
Author :
Mathew, Sanu ; Harris, David ; Anders, Mark ; Hsu, Steven ; Krishnamurthy, Ram
Author_Institution :
Circuits Research Labs, Intel Corporation, Hillsboro, OR 97124, USA
Abstract :
This paper describes a scalable unified reconfigurable 256/1024-bit Encryption Accelerator Montgomery multiplier designed for 2.4GHz operation in 1.2V 90nm process, with total power consumption of 69mW. The design utilizes a fully-static 313ps 256-bit kernel datapath and achieves up to 44% reduction in latency and 50% reduction in FIFO size, enabling 566K 1024-bit finite-field multiplications per second.
Keywords :
CMOS process; Circuits; Delay; Educational institutions; Elliptic curve cryptography; Energy consumption; Hardware; Kernel; Pipelines; Read-write memory;
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
DOI :
10.1109/SOCC.2007.4545418
