A DMOSFET having a cell array field ring for improving avalanche capability

Author

Hoshi, Masakatsu ; Mihara, Teruyoshi ; Matsushita, Tsutomu ; Yao, Kenji ; Sato, Fuminori

Author_Institution

Nissan Motor Co. Ltd., Yokosuka, Japan

fYear

1993

fDate

18-20 May 1993

Firstpage

141

Lastpage

145

Abstract

A DMOSFET having a cell array field ring for improving avalanche capability is described. When shrinking the cell size of the DMOSFET, the cell array field ring is effective for unifying the power dissipation over the chip surface during avalanche breakdown. The power dissipation of this durable DMOSFET is uniform over the chip surface during avalanche breakdown. Its avalanche failure power is around 127 W/mm² for a 1-ms pulse width and tends toward a τ^-1/2 dependence. A failure mechanism during avalanche breakdown is also studied. The critical failure temperature of this DMOSFET is only 50 K lower than the intrinsic temperature for the N-drain regions

Keywords

failure analysis; impact ionisation; insulated gate field effect transistors; power transistors; DMOSFET; Si; avalanche breakdown; cell array field ring; chip surface; critical failure temperature; failure mechanism; power dissipation; power transistor; Automotive applications; Avalanche breakdown; Diodes; Equivalent circuits; Failure analysis; Impurities; Power dissipation; Production engineering; Space vector pulse width modulation; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1993. ISPSD '93., Proceedings of the 5th International Symposium on

Conference_Location

Monterey, CA

ISSN

1063-6854

Print_ISBN

0-7803-1313-5

Type

conf

DOI

10.1109/ISPSD.1993.297125

Filename

297125