DocumentCode
1895690
Title
A merged MuGFET and planar SOI process
Author
Marshall, Andrew ; Cleavelin, C. Rinn ; Xiong, Weize ; Pacha, Christian ; Knoblinger, Gerhard ; Armin, Klaus Von ; Schulz, Thomas ; Schruefer, Klaus ; Matthews, Ken ; Molzer, Wolfgang ; Patruno, Paul ; Russ, Christian
Author_Institution
Texas Instruments Inc., Dallas, USA
fYear
2007
fDate
26-29 Sept. 2007
Firstpage
39
Lastpage
42
Abstract
Tri-gate MuGFET (Multi-Gate FET) offers advantages compared to bulk silicon, with respect to circuit design, but also has some potential drawbacks in thermal effects and width quantization. An advantage of MuGFET is that with the same processing it is possible to make planar SOI structures, which, depending upon the active silicon thickness, may be fully or partially depleted. This work investigates circuit operation on a merged MuGFET and planar SOI process.
Keywords
Annealing; Circuit synthesis; Doping; FETs; History; Hydrogen; Instruments; MOS devices; Quantization; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2007 IEEE International
Conference_Location
Hsin Chu, Taiwan
Print_ISBN
978-1-4244-1592-2
Electronic_ISBN
978-1-4244-1593-9
Type
conf
DOI
10.1109/SOCC.2007.4545421
Filename
4545421
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