Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides

In devices with p+ gates and p- substrates, two unique conditions exist such that the intrinsic and stress-induced traps can be probed and separated in the direct tunneling current. The first condition is that E/sub F/ is initially below the midgap energy of the Si substrate. The second condition is that V/sub fb/ is near V/sub G/=0. Thus, E/sub F/ probes the trap states as it moves up toward E/sub C/. As a result, the increase in the tunneling current between V/sub fb/ and V/sub th/ (e.g., between V/sub G/=0.2 V and 1 V) is a very sensitive measurement of the intrinsic traps and can be used to qualify the initial quality of the oxides. Also under such conditions, the increase of the leakage current due to stress-induced traps can be clearly studied. Therefore, we propose that devices with p+ gates and p- substrates should be used to unify the characterization of ultrathin oxides. In fabricating dual-gate CMOS circuits, such devices can be made to qualify the oxides on product wafers. According to this study, several characteristics of the intrinsic and stress-induced traps can be concluded. Firstly, the intrinsic traps are fast states, and the stress-induced traps (after certain amount of stress) are mostly slow states. Secondly, the trap-assisted tunneling is an elastic process in the direct tunneling regime before stress. Finally, E/sub tr/, and Q/sub tr/, can be estimated from the direct tunneling current. The differences between intrinsic and stress-induced traps should be considered in developing breakdown models for ultrathin oxides.