Lateral depletion-mode thyristors in SOI substrates

The LDMT (lateral depletion-mode thyristor), a new type of lateral MOS-controlled thyristor, is presented. This device is fabricated in a SOI (silicon-on-insulator) substrate, and uses the substrate as back-gate to turn off the thyristor action. The LDMT achieves turn-off via MMCI (MOS-controlled current interruption), whereby the displacement current of an MOS capacitor is used to interrupt the thyristor´s current flow. This device is shown to have a maximum controllable current, in current implementations, which is 8.3 times its holding current. Its switching speed has been measured at less than 600 ns. The authors describe the LDMT and the MCCI mechanism, present experimental results, and discuss the advantages and disadvantages of this device