High packing density power Bi-CDMOS technology and its application for a motor driver LSI

Author

Fujishima, Naoto ; Yano, Yukio ; Nagayasu, Yoshihiko ; Matsuda, Akinori

Author_Institution

Fuji Electric Corp., Res. & Dev. Ltd., Matsumoto, Japan

fYear

1993

fDate

18-20 May 1993

Firstpage

298

Lastpage

303

Abstract

A cost-effective power BiCDMOS process with a 1.5-μm-rule low-voltage CMOS has been realized. A three-layer p-base structure is applied to 35-V n-ch lateral DMOSFETs. The three-layer p-base structure and extended n-drain result in an LDMOSFET with a blocking voltage of 35 V and an on-resistance of 0.28 Ω-mm². A power output layout pattern that reduces the interconnection resistance of power outputs is proposed. The technology has been applied to a spindle and voice coil motor driver LSI with analog and digital signal processing functions for small hard-disk drives. The high-speed and precise bipolar transistors realize accurate signal processing functions

Keywords

BiCMOS integrated circuits; driver circuits; hard discs; large scale integration; mixed analogue-digital integrated circuits; power integrated circuits; 1.5 micron; 35 V; LDMOSFET; blocking voltage; extended n-drain; hard-disk drives; interconnection resistance; lateral DMOSFETs; motor driver LSI; on-resistance; packing density; power BiCDMOS process; power output layout pattern; signal processing functions; three-layer p-base structure; voice coil; Bipolar transistors; CMOS process; CMOS technology; Coils; Digital signal processing; Driver circuits; Hard disks; Large scale integration; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1993. ISPSD '93., Proceedings of the 5th International Symposium on

Conference_Location

Monterey, CA

ISSN

1063-6854

Print_ISBN

0-7803-1313-5

Type

conf

DOI

10.1109/ISPSD.1993.297142

Filename

297142