A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector

A fast pull-in and locking PLL-based frequency synthesizer with a triple-path nonlinear phase frequency detector (TPNPFD) scheme is presented. The proposed scheme can reduce the pull-in time significantly and speed-up the lock-in process. Both the charge pump current and the loop filter capacitors are reduced to 1/k of the conventional ones regardless of the change of the crossover frequency. Moreover a resistor scalar scheme is also presented in this novel architecture.