DocumentCode :
1896057
Title :
A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector
Author :
Lin, Minglang ; Erdogan, Ahmet T. ; Arslan, Tughrul ; Stoica, Adrian
Author_Institution :
School of Engineering and Electronics, University of Edinburgh, EH9 3JL, UK
fYear :
2007
fDate :
26-29 Sept. 2007
Firstpage :
105
Lastpage :
108
Abstract :
A fast pull-in and locking PLL-based frequency synthesizer with a triple-path nonlinear phase frequency detector (TPNPFD) scheme is presented. The proposed scheme can reduce the pull-in time significantly and speed-up the lock-in process. Both the charge pump current and the loop filter capacitors are reduced to 1/k of the conventional ones regardless of the change of the crossover frequency. Moreover a resistor scalar scheme is also presented in this novel architecture.
Keywords :
Capacitors; Charge pumps; Filters; Frequency selective surfaces; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Resistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
Type :
conf
DOI :
10.1109/SOCC.2007.4545437
Filename :
4545437
Link To Document :
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