Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications

A low-power 1.25-GHz signal bandwidth 4-bit ADC designed in a standard 130 nanometer digital CMOS process for high spurious-free dynamic range (SFDR) wideband communications is presented. The ADC uses new clocked digital comparators designed by a dynamic offset suppression technique. The SFDR and ENOB of this 4-bit ADC achieve 31.44 dB and 3.75 bits at input signal of 39 MHz. Near Nyquist frequency input signals, the SFDR and ENOB maintains above 22.79 dB and 2.37 bits at input signal of 1.23 GHz. This ADC has a latency of two and half clock cycles, a low input capacitance of 300 fF, and a low power consumption of 7.9 mW at a 2.5 GHz conversion rate operating down to 120 mV. The ADC has a figure-of-merit (FoM) of 0.611 pJ per conversion step.