A stress-life methodology for ball grid array lead-free and tin-lead solder interconnects under impact conditions

Portable electronic products are often subject to impact or shock during use which leads to failures of the external housing, internal electronic components, package-to-board interconnects, and liquid crystal display panels. Moreover, the introduction of lead-free solder to the electronics industry will bring additional design implications for future generations of mobile information and communication technology (ICT) applications. In this paper, drop tests performed on printed circuit boards (PCBs) populated with ball grid arrays (BGAs) are reported. During testing, measurements from strain gauges were recorded using a high-speed data acquisition system. Electrical continuity through each package was monitored during the impact events in order to detect failure of package-to-board interconnects. Life distributions were established for both a lead-free and a tin-lead solder for various drop heights. The explicit finite element method (FEM) was employed to approximate the peel stress at the critical solder joint and a stress-life model was then established for both solders. Finally, failure analysis was carried out using microsection techniques, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS). It was found that, for board level drop testing, different failure mechanisms can occur for different drop heights and that there is a considerable difference between the lead-free solder characteristic life and the tin-lead solder characteristic life.