A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC

A spur-reduction technique is presented to accomplish low reference spurs while maintaining fast settling time for a fully integrated 5-GHz frequency synthesizer. The proposed synthesizer architecture smoothly adapts the loop parameters according to different operating modes, so as to reduce the loop bandwidth in the locked state to further attenuate the reference spurs. In addition, a high-performance charge pump circuit is incorporated with the adaptive synthesizer to alleviate non-ideal effects that cause spurs. The synthesizer, operating with a supply voltage of 1.2 V in a 0.18-μm CMOS process, achieves a low reference spur level of −60 dBc and a fast settling time of 32 μs for a frequency jump of 220 MHz.