• DocumentCode
    1896137
  • Title

    Programmable CRC circuit architecture

  • Author

    Toal, Ciaran ; Sezer, Sakir ; Yang, Xin ; McLaughlin, Kieran ; Burns, Dwayne ; Seceleanu, Tiberiu

  • Author_Institution
    ECIT Institute, Queen¿s University, Belfast, UK
  • fYear
    2007
  • fDate
    26-29 Sept. 2007
  • Firstpage
    123
  • Lastpage
    126
  • Abstract
    This paper presents the design and implementation of a fully programmable Cyclic Redundancy Check (CRC) computation circuit for System on a Chip (SoC) network processing applications. The presented architecture provides flexibly whilst maintaining gigabit throughput rates for frame/packet processing using standard cell technology.
  • Keywords
    Arithmetic; Circuits; Computer architecture; Concurrent computing; Cyclic redundancy check; Field programmable gate arrays; Polynomials; Protocols; Quality of service; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2007 IEEE International
  • Conference_Location
    Hsin Chu, Taiwan
  • Print_ISBN
    978-1-4244-1592-2
  • Electronic_ISBN
    978-1-4244-1593-9
  • Type

    conf

  • DOI
    10.1109/SOCC.2007.4545441
  • Filename
    4545441
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1896137