Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture

This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algorithms. Out of the decoding algorithms, the modified Min-Sum SPA is selected for implementation and optimization on a reconfigurable instruction cell architecture. Different general and architecture specific optimization techniques are applied to enhance the throughput. With the architecture, a throughput of 20 Mbps has been achieved.