DocumentCode
1896245
Title
H.264/AVC decoder SoC towards the low cost mobile video player
Author
Wisayataksin, Sumek ; Li, Dongju ; Isshiki, Tsuyoshi ; Kunieda, Hiroaki
Author_Institution
Department of Communication and Integrated Systems, Tokyo Institute of Technology, Japan
fYear
2007
fDate
26-29 Sept. 2007
Firstpage
151
Lastpage
154
Abstract
We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications. The SoC, consisting of RISC core and decoder core, has advantages on flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of conventional macroblock or hybrid one, which greatly contribute to reducing drastically the size of the core and its internal memory. The core size is reduced to 138KGate or 36% less and the memory size is reduced to 3.5KB or 65% less than the conventional hybrid pipelining structure. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces are also provided in a chip.
Keywords
Automatic voltage control; Control systems; Coprocessors; Costs; Decoding; Hardware; Pipeline processing; Reduced instruction set computing; SDRAM; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2007 IEEE International
Conference_Location
Hsin Chu, Taiwan
Print_ISBN
978-1-4244-1592-2
Electronic_ISBN
978-1-4244-1593-9
Type
conf
DOI
10.1109/SOCC.2007.4545447
Filename
4545447
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