A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG process

Author

Wakabayashi, H. ; Yamamoto, T. ; Tatsumi, T. ; Tokunaga, K. ; Tamura, T. ; Mogami, T. ; Kunio, T.

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

99

Lastpage

102

Abstract

High-performance 0.1 /spl mu/m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage current and electrical bridging between the gate electrode and S/D regions are suppressed by this high-quality and highly-selective Si-SEG process. The elevated-salicide 0.1-/spl mu/m CMOS devices have high reliability and high drive current, and are suitable for future high-performance logic LSIs.

Keywords

CMOS logic circuits; elemental semiconductors; integrated circuit metallisation; integrated circuit reliability; large scale integration; leakage currents; semiconductor epitaxial layers; semiconductor growth; silicon; vapour phase epitaxial growth; 0.1 micron; 80 nm; CMOS; SEG process; Si; drive current; electrical bridging; elevated salicide; gate electrode; gate side-wall; high-performance logic LSIs; junction leakage current; reliability; selective epitaxial growth; source/drain region; CMOS logic circuits; CMOS process; Epitaxial growth; Laboratories; Leakage current; MOSFETs; P-n junctions; Semiconductor films; Silicon; Surface morphology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649473

Filename

649473