Title :
Mixed-VTH (MVT) CMOS circuit design for low power cell libraries
Author :
Lin, Jiun-Yi ; Wang, Li-Rong ; Hu, Chia-Lin ; Jou, Shyh-Jye
Author_Institution :
Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, China
Abstract :
Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.
Keywords :
CMOS logic circuits; CMOS technology; Circuit synthesis; Design methodology; Energy consumption; Leakage current; Libraries; Logic circuits; MOSFETs; Threshold voltage;
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
DOI :
10.1109/SOCC.2007.4545454
