Title :
Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 /spl mu/m CMOS technologies
Author :
Chao, C.-P. ; Violette, K.E. ; Unnikrishnan, S. ; Nandakumar, M. ; Wise, R.L. ; Kittl, J.A. ; Hong, Q.-Z. ; Chen, I.-C.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Raised source/drain (R/SD) CMOS transistors with Co or Ti salicide to improve narrow-poly sheet resistance and diode leakage are studied. At 0.11 /spl mu/m gate length, low resistance of 2 /spl Omega//sq and 1.2 /spl Omega//sq are achieved for CoSi/sub 2/ (with 400 /spl Aring/ R/SD) and TiSi/sub 2/ with 700 /spl Aring/ R/SD and pre-amorphization implant (PAI), respectively. These results are due to the lateral over-growth of the deposited silicon to form T-shaped gates. Significant improvement in the junction leakage current is also observed for the R/SD devices with CoSi/sub 2/ salicide. Comparison of integration issues such as silicide bridging, poly depletion, and gate oxide integrity are presented together with transistor drive current and source/drain series resistance.
Keywords :
CMOS integrated circuits; MOSFET; cobalt compounds; integrated circuit metallisation; ion implantation; leakage currents; titanium compounds; 0.11 micron; 400 angstrom; 700 angstrom; CMOS technologies; CoSi/sub 2/; T-shaped gates; TiSi/sub 2/; diode leakage; gate length; gate oxide integrity; junction leakage current; lateral over-growth; narrow-poly sheet resistance; poly depletion; pre-amorphization implant; raised source/drain transistors; silicide bridging; source/drain series resistance; transistor drive current; CMOS technology; Chaos; Degradation; Drives; Implants; Instruments; Leakage current; Semiconductor diodes; Silicides; Silicon;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.649474
