Title :
A 45nm dual-port SRAM with write and read capability enhancement at low voltage
Author :
Wang, D.P. ; Liao, H.J. ; Yamauchi, H. ; Chen, Y.H. ; Lin, Y.L. ; Lin, S.H. ; Liu, D.C. ; Chang, H.C. ; Hwang, W.
Author_Institution :
Institute of EE, National Chiao-Tung University, Taiwan
Abstract :
This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.
Keywords :
Boosting; CMOS technology; Circuits; Logic; Low voltage; MOS devices; Random access memory; SRAM chips; Variable structure systems; Writing;
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
DOI :
10.1109/SOCC.2007.4545460
