DocumentCode :
1896845
Title :
RIFFA 2.0: A reusable integration framework for FPGA accelerators
Author :
Jacobsen, Matthew ; Kastner, Ryan
Author_Institution :
Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
fYear :
2013
fDate :
2-4 Sept. 2013
Firstpage :
1
Lastpage :
8
Abstract :
We present RIFFA 2.0, a reusable integration framework for FPGA accelerators. RIFFA 2.0 provides communication and synchronization for FPGA accelerated applications using simple interfaces for hardware and software. Our goal is to expand the use of FPGAs as an acceleration platform by releasing, as open source, a framework that easily integrates software running on commodity CPUs with FPGA cores. RIFFA 2.0 uses PCIe to connect FPGAs to a CPU´s system bus. RIFFA 2.0 extends the original RIFFA project by supporting more classes of Xilinx FPGAs, multiple FPGAs in a system, more PCIe link configurations, higher bandwidth, and Linux and Windows operating systems. This release also supports C/C++, Java, and Python bindings. Tests show that data transfers between hardware and software can saturate the PCIe link to achieve the highest bandwidth possible.
Keywords :
field programmable gate arrays; logic design; synchronisation; C/C++; FPGA accelerated applications; FPGA accelerators; FPGA cores; Java; Linux operating system; PCIe link configurations; Python bindings; RIFFA 2.0; Windows operating system; Xilinx FPGA; acceleration platform; commodity CPU; data transfers; open source; reusable integration framework; synchronization; system bus; Acceleration; Clocks; Field programmable gate arrays; Hardware; Protocols; Software; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
Conference_Location :
Porto
Type :
conf
DOI :
10.1109/FPL.2013.6645504
Filename :
6645504
Link To Document :
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