Assertion based design error diagnosis for core-based SoCs

In this paper, we propose an assertion based methodology for diagnosing design errors inside a core-based SoC. In order to detect errors inside a core we have a sea of assertions together with a Local Assertion Processor (LAP) to handle the outputs of these assertions and diagnose the error position. The outputs of assertions are routed toward this processor through a boundary scan chain mechanism. After detecting and diagnosing the error, each LAP sends a specific data called error data to a Global Assertion Processor (GAP) which receives error data from all cores and performs necessary actions. We applied the proposed method on a simple multiprocessor SoC and showed the experimental results.