Title :
Charge recycling for power reduction in FPGA interconnect
Author :
Huda, S. ; Anderson, Jon ; Tamura, H.
Author_Institution :
Dept. of ECE, Univ. of Toronto, Toronto, ON, Canada
Abstract :
We propose charge recycling (CR) to reduce power consumption in FPGAs. We take advantage of the property that many routing conductors are left unused in any FPGA implementation of an application. Charge recycling via the unused conductors reduces the amount of charge drawn from the supply, lowering energy consumption. We present a routing switch that operates in two modes: normal and CR, and describe the CAD tool changes needed to support CR at the routing and post-routing stages of the flow. Results show that dynamic power in the FPGA interconnect can be reduced by up to ~15-18.4% by the proposed techniques, depending on the performance constraints.
Keywords :
CAD; field programmable gate arrays; integrated circuit interconnections; logic design; power consumption; CAD; FPGA interconnect; charge recycling; power consumption; power reduction; routing conductors; routing switch; Conductors; Field programmable gate arrays; Recycling; Reservoirs; Routing; Switches; Wires;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
Conference_Location :
Porto
DOI :
10.1109/FPL.2013.6645509