DocumentCode
1897859
Title
A new economical wafer drying technology with high process performance
Author
Asada, Kazumi ; Iwamoto, Hayato ; Hashiguchi, Toshiya ; Okamoto, Yutaka ; Minami, Teruomi ; Ueno, Kinya ; Kitahara, Saori
Author_Institution
Semicond. Co., Sony Corp., Kanagawa, Japan
fYear
1997
fDate
6-8 Oct 1997
Abstract
Requirements for a Si wafer cleaning and drying technology with better performance and better cost efficiency, as well as less environmental pollution are on the increase, as the wafer diameter becomes larger and the pattern design rule becomes as small as 0.25 μm and below. The conventional IPA vapor dryers are widely used for wafer drying today, however, this method requires a large amount of IPA. Here, we report a new drying method (Stacked Dual Chamber Dry) using a small amount of IPA vapor in inert gas. It was found that the new drying method consumes one-fourth of the IPA with conventional drying and processing time is significantly shortened
Keywords
drying; elemental semiconductors; semiconductor technology; silicon; surface cleaning; 0.25 mum; IPA; IPA residue; IPA vapor dryers; IPA vapour; Si; Si wafer cleaning; Si wafer drying; Stacked Dual Chamber Dry; cost efficiency; economics; environmental pollution; pattern design; performance; wafer diameter; wafer drying; watermark; Chemical processes; Cleaning; Costs; Electrons; Environmental economics; Pollution; Temperature control; Temperature sensors; Testing; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-3752-2
Type
conf
DOI
10.1109/ISSM.1997.664555
Filename
664555
Link To Document