Title :
Net assignment in gate matrix layout
Author :
Rim, Chong S. ; Nakajima, Kazuo
Author_Institution :
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Abstract :
In the gate matrix layout approach for CMOS circuits, columns are first rearranged so as to minimize the number of rows needed. This problem is known to be NP-hard. When this is completed, the sets of nets and vertical diffusion runs are determined. The next problem is to assign the nets to rows so that the gate matrix can by physically laid out with minimum area. It is shown that this problem is also NP-hard and a heuristic algorithm is proposed for this problem.<>
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; minimisation; CMOS circuits; NP complete problems; NP hard problems; columns rearrangement; gate matrix; gate matrix layout; heuristic algorithm; minimum area; net assignments; row minimisation; sets of nets; vertical diffusion runs; Circuits; Educational institutions; Heuristic algorithms; Strips;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.15029
