Aging-based leakage energy reduction in FPGAs

Author

Sheng Wei ; Zheng, Jinxing ; Potkonjak, Miodrag

Author_Institution

Comput. Sci. Dept., Univ. of California, Los Angeles (UCLA), Los Angeles, CA, USA

fYear

2013

fDate

2-4 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.

Keywords

ageing; computability; field programmable gate arrays; logic design; negative bias temperature instability; FPGA; ITC99 benchmarks; NBTI aging; Opencores benchmarks; PV; SAT problem; Xilinx Spartan6 FPGA design; aging-based leakage energy reduction; deep submicron technology; low energy design; negative bias temperature instability; post-silicon leakage energy optimization scheme; process variation; satisfiability problem; Aging; Field programmable gate arrays; Logic gates; MOSFET; Threshold voltage; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on

Conference_Location

Porto

Type

conf

DOI

10.1109/FPL.2013.6645562

Filename

6645562