Title :
0.25 μm integrated circuit yield model design and validation
Author :
Lakhani, Fred ; Dance, Daren ; Williams, Randy
Author_Institution :
SEMATECH, Austin, TX, USA
Abstract :
This paper provides an overview of the design and the methods used to establish validated defect density targets for a 0.25 μm process tool set based on a new SEMATECH yield model. This is the first model to provide industry tool targets derived from real manufacturing data. Besides the model design and the model validation approach, the paper provides particles per wafer pass (PWP) tool targets (for top ten yield detractors) to achieve 90%, random defect limited yield (RDLY) for a 0.25 μm logic process. Future work to optimize the model further is outlined as well
Keywords :
integrated circuit modelling; integrated circuit yield; integrated logic circuits; 0.25 micron; SEMATECH yield model; industry tool targets; integrated circuit yield; logic process; particles per wafer pass; random defect limited yield; validated defect density targets; yield model design; Circuit faults; Design methodology; Inspection; Integrated circuit modeling; Integrated circuit yield; Logic; Pulp manufacturing; Semiconductor device modeling; Virtual manufacturing; Yield estimation;
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-3752-2
DOI :
10.1109/ISSM.1997.664557
