DocumentCode
1898446
Title
Multiplication by an integer using minimum adders
Author
Dempster, A.G. ; Macleod, M.D.
Author_Institution
Dept. of Eng., Cambridge Univ., UK
fYear
1994
fDate
34375
Firstpage
42675
Lastpage
42678
Abstract
A graph representation of multiplier blocks has been described by Bull and Horrocks (IEEE Proc.G. vol.138, no.3, p.401-12, June 1991) for the design of finite impulse response (FIR) digital filters. This graph representation is applied to the problem of reducing the number of adders in a constant integer multiplier
Keywords
adders; digital arithmetic; digital filters; graph theory; IEEE Proc.G.; constant integer multiplier; finite impulse response digital filters; graph representation; minimum adders; multiplier blocks;
fLanguage
English
Publisher
iet
Conference_Titel
Mathematical Aspects of Digital Signal Processing, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
297467
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