A 0.5μm CMOS/SOI technology

Author

Edenfeld, A. ; Wang, L.K. ; Seliskar, J. ; Haddad, N.

Author_Institution

IBM Federal Sector Div., Manassas, VA, USA

fYear

1991

fDate

1-3 Oct 1991

Firstpage

130

Lastpage

131

Abstract

The authors describe a 0.5-μm fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5-μm CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the `kink effect´ and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1×10¹⁵. The I-V characteristics of the n- and p-MOSFETs are shown

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit technology; integrated logic circuits; semiconductor-insulator boundaries; 0.5 micron; 100 nm; I-V characteristics; SIMOX; SRAM; Si-SiO₂; accumulation mode device design; anomalous subthreshold current elimination; background doping level; circuit performance; floating substrate; fully depleted CMOS; fully depleted FET design; kink effect elimination; lightly doped substrate; logic applications; thickness; thin SOI film; CMOS logic circuits; CMOS technology; Circuit optimization; Doping; FETs; Logic devices; MOSFET circuits; Random access memory; Substrates; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1991. Proceedings, 1991., IEEE International

Conference_Location

Vail Valley, CO

Print_ISBN

0-7803-0184-6

Type

conf

DOI

10.1109/SOI.1991.162891

Filename

162891