Low-power column-parallel ADC for CMOS image sensor by leveraging spatial likelihood in natural scene

This paper presents the architecture, algorithm and implementation of a low-power column-parallel analog-to-digital converter (ADC) for CMOS image sensor. The analysis of most natural scenes shows that neighbor pixels have strong correlations. In this paper, a prediction scheme was proposed based on this spatial likelihood in natural scenes. The scheme predicts the MSBs of the selected pixel using previous-row pixel A/D conversion data, which enables significant reduction of A/D conversions steps on MSBs and the power consumption. The simulation results show that up to 20%-30% power saving can be achieved for most natural scenes. A prototype CMOS image sensor (CIS) chip, including a 98×98 pixel array and a 9-bit column-parallel successive approximation register (SAR) ADC array, was fabricated using 0.35μm CIS technology. The silicon size is 3.5×1.8 mm².