DocumentCode
1898971
Title
High Performance BFL Frequency Divider Development
Author
Gavant, M. ; Perea, E.H.
Author_Institution
Thomson-Semiconductors (DHM), Route Départementale 128 /BP 48, 91401 ORSAY CEDEX (FRANCE)
fYear
1987
fDate
23-25 Sept. 1987
Firstpage
225
Lastpage
228
Abstract
We report the development and performance measurement of packaged frequency dividers by 2 and 4. A typical range of 100 MHz to 3 GHz has been covered for a smaller than 0 dBm sinewave input signal, and for ambient temperature of 125 C. The basic cell is a single clock master-slave flip-flop designed in BFL logic. Functional wafer probing at 2GHz shows 85% typical yields.
Keywords
Circuits; Clocks; Diodes; Flip-flops; Frequency conversion; Frequency synthesizers; Packaging; Temperature distribution; Temperature sensors; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-state Circuits Conference, 1987. ESSCIRC '87. 13th European
Conference_Location
Taunus-Tagungs-Zentrum, F.R. Germany
Print_ISBN
3800715341
Type
conf
Filename
5434914
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