Analysis of matrix multiplication on high density Virtex-7 FPGA

In this work, we have developed a theoretical model of matrix multiplication including a detailed model of external memory access. We have used the model to guide the design of a many core architecture. The architecture was modeled and simulated in SystemC and a small prototype was implemented in an FPGA board to determine the accuracy of the model. Finally, using the model, we determined the achievable performance in Virtex-7 FPGAs. The results indicate the correctness of the model and the performance of state-of-the-art FPGAs in the execution of matrix-multiplication.