• DocumentCode
    1899715
  • Title

    Rapid modular assembly of Xilinx FPGA designs

  • Author

    Love, A. ; Athanas, Peter

  • Author_Institution
    Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2013
  • fDate
    2-4 Sept. 2013
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow consists of a rapid method for design assembly, decoupled from the vendor tools. This enables software-like turnaround time for faster prototyping and increased productivity.
  • Keywords
    field programmable gate arrays; logic design; rapid prototyping (industrial); GReasy front-end; TFlow back-end; Xilinx FPGA designs; back-end time; design assembly; field programmable gate arrays; rapid modular assembly; rapid prototyping; Assembly; Binary phase shift keying; Field programmable gate arrays; Hardware design languages; Libraries; Productivity; Software;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
  • Conference_Location
    Porto
  • Type

    conf

  • DOI
    10.1109/FPL.2013.6645620
  • Filename
    6645620
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1899715