Title :
From Quartus to VPR: Converting HDL to BLIF with the Titan flow
Author :
Murray, Kevin E. ; Whitty, Scott ; Liu, Siyuan ; Luu, Jason ; Betz, Vaughn
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD tools.
Keywords :
field programmable gate arrays; logic design; BLIF; CAD evaluation; FPGA architecture; HDL; Quartus; Titan flow; VPR; academic CAD tools; Benchmark testing; Computers; Cryptography; Design automation; Field programmable gate arrays; Hardware design languages; IP networks;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
Conference_Location :
Porto
DOI :
10.1109/FPL.2013.6645626
