Title :
Design rule methodology to improve the manufacturability of the copper CMP process
Author :
Lakshminarayanan, S. ; Wright, Peter ; Pallinti, Jayanthi
Author_Institution :
Process Technol. Dev., Santa Clara, CA, USA
Abstract :
A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due to line width and pattern density effects is characterized for single and multi-level interconnects and the feature interaction distance is determined to be about 30 μm. It is shown that the best way to minimize the sheet resistance spread is by implementing rules for the minimum and maximum space between any two features as a function of their widths.
Keywords :
chemical mechanical polishing; copper; design for manufacture; electric resistance; integrated circuit interconnections; integrated circuit layout; integrated circuit measurement; integrated circuit metallisation; 30 micron; Cu; Cu CMP process manufacturability improvement; copper chemical mechanical polishing process; damascene metal layers; design robustness; design rule methodology; feature interaction distance; feature width; intra-die sheet resistance variation; layer design rules; layout guidelines; line width effects; maximum feature space; minimum feature space; multilevel interconnects; pattern density effects; sheet resistance minimization; single level interconnects; Clocks; Copper; Design methodology; Integrated circuit interconnections; Large scale integration; Logic design; Manufacturing processes; Robustness; Surfaces; Testing;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014900
