Title :
A simulation method for predicting packaging mechanical reliability with low κ dielectrics
Author :
Mercado, Lei ; Goldberg, Cindy ; Kuo, Shun-Meen
Author_Institution :
Motorola Final Manuf. Technol. Center, Tempe, AZ, USA
Abstract :
It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.
Keywords :
ball grid arrays; ceramic packaging; copper; delamination; flip-chip devices; fracture mechanics; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; internal stresses; microassembling; plastic packaging; CBGA; Cu; Cu/low-k flip-chip packages; Cu/low-k structures; PBGA; ceramic ball grid array packages; critical failure locations; die attach process; four-level models; interface delamination; interface fracture mechanics; multi-level multi-scale modeling technique; package level; packaging mechanical reliability; plastic ball grid array packages; simulation method; thin film residual stresses; wafer level; Copper; Delamination; Dielectrics; Electronics packaging; Microassembly; Plastic films; Predictive models; Residual stresses; Semiconductor device modeling; Wafer scale integration;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014907
