A methodology for the interconnect performance evaluation of 2D and 3D processors with memory

Stochastic wire length distribution models often overlook the presence of a large amount of on-chip memory, treating it as random logic. Based on layout considerations for the memory, a methodology for interconnect performance evaluation is proposed that takes the memory into account. It is shown that not taking the complete model can lead to erroneous results. The benefits of 3D integration are then evaluated with different possible arrangements of memory on different active layers.